The present invention relates to a method for fabricating a structure which provides for the modulation of surface electrostatic fields over very short distances which may be applied to the fabrication of semiconductor devices.
The development of faster and faster electronic circuits and devices has been achieved through increasingly smaller devices and spacings between the elements comprising each device. Speed reductions have resulted from the reduction of electron or hole transit times due to the reduced distances, but as the development of advanced lithographic tools progressed to the point where patterns were transferable at lateral dimensions approaching tenth's of microns, quantum effects, such as ballistic overshoot, hot carrier effects, etc., had to be considered in the operation and design of these devices.
The development of various fabrication tools that allowed for the artificial structuring of materials on a vertical scale at the atomic level expanded the scope of even smaller and faster devices which could be fabricated. These tools included MBE (Molecular Beam Epitaxy), MOCVD (Metal-Organic Chemical Vapor Deposition), and other variants.
Significant research efforts in the field of heterostructure transistors have led to developments where it became possible to confine carriers in atomically smooth layers as thin as 80.ANG., the width of the electron(/hole) wave function itself, and to observe transport parallel to the confined layer. These efforts resulted in the MODFET (Modulation-Doped Field-Effect Transistor, also referred to as HFET and TEGFET), where carriers are believed to move within a two-dimensional electron (hole) gas and are confined parallel to the plane of the device in a "carrier sheet." This device requires efficient modulation of the underlying carriers beneath the "gate" of the device. The typical method for achieving this is to place metal electrodes on the surface of the device, and electrostatically couple the potentials on these electrodes to the channel.
The desire to have multiple gates on the surface shortly became evident. It was found that the efficiency of a device might be improved by utilizing two gates placed as closely as possible, instead of one, resulting in the split-gate MODFET. Successful fabrication of a vertical lateral resonant tunneling transistor lead to proposal of a lateral version, i.e., the lateral resonant tunneling transistor. However, to take full advantage of the quantum nature of this carrier sheet, described in the preceding paragraph, the electrodes should ideally be placed as close as possible.
The most common means for fabricating a small line on a semiconductor substrate is to utilize PolyMethylMethAcrylate (PMMA) or other electron-beam resist, expose it using an electron beam, develop the pattern, and transfer the pattern to a metal or semiconductor layer using standard liftoff or etching techniques. However, due to the existence of backscattered electrons and finite contrast value in the PMMA, single line/dot dimensions are limited to near 300.ANG..Should one desire a line-space array, the resolution is limited to perhaps line widths of 500.ANG., separated by about 500 .ANG..
These resolution limitations were acceptable a number of years ago. However, with processing advances and a growing interest in quantum sized devices, methods for producing even smaller lateral dimensions are desired. It appears that the limits of electron beam fabrication techniques alone have been reached. STM (Scanning Tunneling Microscope) techniques have been for moving individual atoms; however, the STM technique is very slow and not presently employable in a mass production environment. In addition, the fabrication of lines closely spaced presents another problem in actual operation. If the lines are spaced closely enough, an insulator must be placed between them to prevent catastrophic arcing between electrodes on the surface.
A need exists for a technique for manufacturing a structure which has electrodes spaced at dimensions at less than 300 to 500.ANG..